1. Field of the Invention
The present invention relates generally to state retention of an integrated circuit, and
more particularly to leveraging a clock network shielding to distribute a state retention supply voltage to state retention devices on the integrated circuit.
2. Description of the Related Art
Low Power consumption is emerging as a very important feature for many handheld and battery powered applications. In conventional configurations, however, low power design was not free and added considerable overhead in both silicon area and routing. In particular, an application may be configured with one or more low power states in which only a subset of the components remain powered on to maintain the state of the device. The state retention devices are typically distributed throughout the chip or integrated circuit (IC). In the conventional configuration, a state retention supply voltage was distributed to the state retention devices using a separate state retention power grid. The state retention power grid consumed significant routing resources and reduced the available space for functional components. Further, the state retention power grid often required additional metal layers complicating design and substantially increasing cost.